Abstract
The optimization of test node selection is key stage for analog circuits test modes. In this master thesis, optimization technique was studied for test node selection based on Ants Colony Algorithms. The studied technique can yield high faults detection and isolation rates with less number of nodes. The methods, used to select test nodes for fault isolation, such as Heuristic method, Ambiguity sets method and Hashing Method were discussed. The studied concepts can also be applied in the domain of fault dictionary approach for optimization purposes.
